The present invention relates in general to a method of coating a surface of a substrate with a metal, and more particularly copper, by electroplating, in particular a surface consisting of an electrically resistive material.
The invention is especially applicable in the field of microelectronics for the fabrication of interconnects in integrated circuits. It is also applicable in other fields of electronics, for the fabrication of interconnects in printed circuits (called printed circuit boards or printed wire boards) or for the fabrication of passive elements, such as inductors, or in the electromechanical field in integrated circuits or in microsystems (called microelectromechanical systems).
The term “electroplating” is understood here to mean a method of covering a surface of a substrate with a metallic or organometallic coating, in which the substrate is electrically biased and brought into contact with a liquid that contains precursors of the said metallic or organometallic coating, so as to form the said coating. When the substrate is an electrical conductor, the electroplating is for example carried out by passing a current between the substrate to be coated which constitutes an electrode (the cathode in the case of a metallic or organometallic coating) and a second electrode (the anode) in a bath containing a source of precursors of the coating material (for example metal ions in the case of a metallic coating) and optionally various agents intended to improve the properties of the coating formed (uniformity and fineness of the deposit, resistivity, etc.), optionally with a reference electrode being present. By international convention, the current flowing through and the voltage applied to the substrate of interest, that is to say the cathode of the electrochemical circuit, are negative. Throughout this text, when these currents and voltages are mentioned with a positive value, it is implicit that this value represents the absolute value of the said current or the said voltage.
Copper electroplating is used in particular in the microelectronics field for the fabrication of interconnects in integrated circuits. The good electrical conductivity of copper and its high resistance to the phenomenon of electromigration, that is to say the low migration of copper atoms under the effect of the electric current density that can be responsible to significantly deform the conductor and be a major cause of failure, makes it in particular a material of choice for the fabrication of metal interconnects for integrated circuits of increasingly smaller etched features.
Integrated circuits are generally fabricated by forming active semiconductor devices, especially transistors, on the surface of silicon wafers, the said semiconductor devices being connected together by a system of metal interconnects consisting of “lines” and “contacts”, also called “vias” placed in superimposed levels and obtained by respectively filling “trenches” and “wells” also called “interconnection holes”, made in the dielectric layers.
Since copper is difficult to etch and has a high diffusivity in many materials, the interconnects are generally produced by a sequence of steps comprising:                deposition of an insulating dielectric layer;        etching of the interconnect features in the said dielectric layer;        deposition of a barrier layer (generally made of tantalum, titanium nitride, tantalum nitride, tungsten nitride or tungsten carbide, for example) used to prevent copper migration;        filling of the lines and interconnection holes with copper; and        removal of the excess copper by chemical mechanical polishing.        
This sequence of steps is known by the name “Damascene process”, which has been described for example by C. Y. Chang and S. M. Sze “ULSI Technology”, McGraw-Hill, New York, (1996), pages 444-445.
The barrier layer generally has too high a resistance for copper to be electrochemically deposited homogeneously or uniformly at the wafer scale, an effect known to those skilled in the art by the term “ohmic drop”. The high resistance of the barrier layer results both from the high resistivity of its constituent materials (generally metal nitrides) and from its small thickness (generally from a few nm to a few tens of nm, depending on the integrated circuit generation), which thickness is imposed by the small size of the interconnect features.
Consequently, it is generally necessary, prior to the copper electroplating step, to cover the barrier layer —using a non-electrochemical method—with a thin layer of metallic copper, called a seed layer. This seed layer, like the barrier layer, is currently produced by vapor phase deposition techniques such as PVD (physical vapor deposition) or CVD (chemical vapor deposition) deposition processes.
Owing to the critical dimensions of the lines and interconnection holes of current integrated circuits, and their trend towards ever smaller dimensions, the thickness of the copper seed layers at the present time is around 30 nm and should rapidly move towards 10 nm or less.
CVD deposition produces a conformal copper layer, that is to say one that accurately matches the topography of the surface to be coated, and does so for a wide range of aspect ratios. However, the adhesion to the diffusion barriers of the copper layers formed by chemical deposition is poor. This limits in practice the benefit of this type of process since as strong adhesion between the copper and the barrier is required in order to ensure reliability of the structures constituting the interconnects.
In addition, processes using chemical vapor deposition are relatively expensive because of the high cost of the consumables (the precursors), of the equipment needed to implement them and their low efficiency.
PVD deposition is presently preferred from the industrial standpoint because it allows surfaces having a high resistance to be coated with better adhesion of the copper to the barrier than obtained with CVD processes.
The thickness of the coating deposited by PVD is directly proportional to the solid angle seen from the surface to be coated. Consequently, those portions of the surface having salient angles are covered with a thicker layer than those portions of the surface having re-entrant angles. As a result, the copper seed layers formed by physical vapor deposition are not conformal, and therefore do not have a uniform thickness at every point on the surface of the substrate. In particular, shadow or overhang effects are observed at the sharp edges of trenches or vias, up to the point of obstructing their apertures and then making it impossible to fill them. Moreover, the sidewalls of the trenches and vias may be covered with an insufficient thickness of the seed layer, which then results in imperfect subsequent filling, missing material or voids. In addition, the seed layer produced on the sidewalls of the features exhibits by nature an adhesion that differs from that deposited on the flat surface of the substrate (at the top and bottom of the trenches and vias). This may lead to inferior reliability properties, such as resistance to electromigration. In other words, the non-conformal coverage does not solely result in differences in thickness as lack of continuity and poor adhesion of the layer on the sidewalls of the trenches and vias may also arise therefrom.
These limitations make it very tricky to use PVD technology in advanced generation integrated circuits with very small dimensions of the trenches and vias (of the order of a few tens of nanometers) and very high aspect ratios.
In this context, the electroplating technique presented here constitutes an advantageous alternative to chemical vapor deposition or physical vapor deposition processes, and to the more conventional metal electroplating techniques, which cannot be implemented on resistive substrates.
This is because conventional electroplating, which consists in applying in general a DC current to the substrate immersed in a bath containing metal ions, can be applied only to surfaces that are sufficiently conducting, that is to say typically having a sheet resistance of less than about a few ohms/square, which is not the case for the layers forming a copper diffusion barrier in the most advanced technologies, the sheet resistance of which is commonly a few tens of ohms/square to several hundred ohms/square and may be several tens of thousands of ohms/square.
Sheet resistance is a quantity used by those skilled in the art for measuring electrical resistance of thin films or layers. It is expressed in ohms/square and is equivalent to the resistivity for a two-dimensional system, that is to say one in which the current flows in the plane of the layer and not in a plane perpendicular to this layer. Mathematically, the value of the sheet resistance is obtained by dividing the resistivity (expressed in ohms·m or microohms·cm) of the constituent material of the layer by the thickness (expressed in m or nm) of this layer.
At the present time, conventional copper electroplating is mainly used for filling the trenches and wells in the damascene process by applying a DC current to a wafer covered beforehand with a seed layer and immersed in an acid copper sulphate bath containing additives. This process for filling the trenches and wells with metallic copper is described for example by Rosenberg et al., in “Copper metallization for high performance silicon technology”, Ann. Rev. Mater. Sci (2000), 30, 229-62.
The use of copper electroplating on a copper seed layer for filling trenches and wells has also been described in U.S. Pat. No. 6,893,550 incorporated herein by reference.
The electroplating method described in document U.S. Pat. No. 6,893,550 is essentially characterized:                on the one hand, in that it makes use of an electroplating bath whose specific chemical composition comprises at least one acid, preferably sulphuric acid, at least one halide ion, preferably chloride, and a combination of chemical agents capable of accelerating or suppressing formation of the coating; and        on the other hand, in that it consists in modifying the density of the current applied in predetermined sequences.        
Copper electroplating has also been recommended, for example in U.S. Pat. No. 6,811,675, for filling any voids in the seed layer (seed enhancement) or for repairing this layer (seed repair).
In a preferred embodiment described in this prior document, a first step is carried out, preferably by a physical vapor deposition process, in which a non-uniform “ultrathin” (thickness of about 20 nm) copper seed layer is deposited and then in a second step the conformality of the layer is improved by electroplating using an alkaline electroplating solution (the pH of which is greater than 9) containing copper sulphate, a copper complexing agent, preferably citric acid, and optionally boric acid in order to improve the brightness of the coating and/or ammonium sulphate for reducing the resistivity of the coating. The DC current density applied during electroplating is between 1 mA/cm2 and 5 mA/cm2.
It is indicated in the above prior document that this electroplating process may also be used to produce a copper seed layer directly, but this possibility is not illustrated by any example and it appears not to be easily achievable owing to the high current densities mentioned in that document.